Control codes, for example, Error Correction Codes (ECC), are commonly used for improving the reliability of a memory device, such as a flash E2PROM with multilevel cells. As known, a multilevel cell can take a number of states higher than two (to each one is associated a corresponding logic value). Typically, the number of states is equal to a power of 2, with a cell supporting 2N states storing N bits of information. Each state is defined by a respective range of a specific physical quantity (for example, a voltage).
However, the increased number of possible states for the memory cell involves a reduction of the voltage ranges associated with each logic value (for the same voltage window that is available for operating the memory cell). This makes the device more sensitive to noise, since a lower voltage change can bring about the reading of a wrong logic value.
The error correction codes add redundant information to every predetermined set of bits (a page). Such redundant information is used to detect and correct (if possible) any errors in the page. This allows some defective cells to be accepted in the memory device without jeopardizing its operation. In this way, the production cost of the memory device can be significantly reduced.
However, the above-described structure requires the reading of a whole page (to verify its correctness), before the bits contained therein can be used. This results in some constraints on the operation of the memory device, for example, in the case of reading in the burst mode wherein the information required is output in succession at every clock signal.
In fact, when the reading in the burst mode involves a set of bits between two consecutive pages, both pages must be read completely before outputting the required information. This calls for the introduction of wait cycles, which slows down operation of the memory device.
A possible approach to such a drawback would be to read two consecutive pages in parallel (for example, an even page and an odd page). Nevertheless, in a standard decoding structure each reading element is selectively connected to a memory cell of an associated set (through selection elements controlled by the same signals for all the sets). Therefore, this also does not allow the reading in the burst mode of a set of bits between an odd page and an even page.
A different decoding structure (known as smart decoding) has been proposed for performing readings in the burst mode from any position in a memory device with cells only supporting two levels. In this structure, alternative paths are added so as to allow memory cells in different positions in each set to be reached at the same time. However, this requires the introduction of additional selection signals. Moreover, the management of these selection signals is rather complex and involves substantial changes to the operation of the memory device. Finally, the proposed decoding structure cannot be readily applied to a memory device with multilevel cells.